Information: info@dresd.org

.:: Project Description ::.

Recent advances in VLSI technology show the limits of the classical and widely--used computation--centric design paradigm of embedded--systems. The ever increasing level of integration and complexity in digital electronic systems ensured by Moore's Law requires a novel design paradigm: a communication--centric approach. Communication is becoming more and more relevant from the performance perspective, since the increasing number of modules (attached IP--Cores) leads to even more stressing communication requirements.

Aim of this work is to propose a novel run-time reconfigurable Netwrok on Chip framework based on the partial dynamic reconfiguration capabilities of Field-Programmable Gate Arrays (FPGAs).The proposed approach can be easily adapted to different scenarios in order to provide the designer with the best fitting communication infrastructure for each of them.

.:: Involved Institutes ::.

.:: Politecnico di Milano
.:: EPFL



.:: DRESD documentation about this project ::.

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