Information: info@dresd.org

Who: Prof. Seda Ogrenci Memik, Northewestern Univerisy

.:: Abstract ::.

The impact of temperature on integrated chips is multifaceted. Temperature has a direct impact on the reliability of the chips. High temperature accelerates gate dielectric layer deterioration and the electromigration process, greatly reducing the mean time to failure of the chips. Temperature also plays a dual role on circuit performance. It decreases the mobility of the charge carriers, leading to degraded gate and interconnect performance. On the other hand, high temperature decreases the threshold voltage, resulting in improved performance of the CMOS gates. Such a sophisticated relation between temperature and timing complicates the circuit synthesis and verification flow. Finally, leakage power consumption, which can be the major contributor to the total power consumption for deep submicron designs, has a strong dependence on temperature. The PN junction reverse-bias current increases with increasing temperature in an exponential fashion, and the subthreshold leakage current, which dominates modern device off-state leakage due to the low Vth, is a strong function of temperature as well.

Resolving the thermal issue requires a systematic treatment across multiple design levels. In this talk Dr. Ogrenci Memik will present recent solutions developed by her research team to address the thermal issues in high performance chips. The two key aspects presented in this talk are monitoring and mitigation. Thermal monitoring mechanisms help the thermal management system to predict and detect the thermal emergencies. Dr. Ogrenci Memik will present an overview of the design of a novel integrated thermocouple array based thermal sensor. Thermal mitigation involves system- and microarchitecture level approaches, which help reducing the temperature of the hot spots. A framework for optimizing an active cooling system will be presented as part of this research direction.