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Reconfigurable Computing Italian Meeting
The first edition of the Reconfigurable Computing Italian Meeting will be held in room S01 - Politecnico di Milano, Milano, Italy. This workshop aims at creating an event where all the people interested in the reconfigurable computing area (Universities, Companies, Research Institutes and also single people), can present their works and ideas, discussing future trends in the Reconfigurable Computing field.


How to participate
The meeting is completely free of charge. In order to attend the meeting, please send an email to rcim@dresd.org. If you also would like to have an active role in the meeting (e.g., presenting your work, promoting possible cooperation or presenting your needs), please get in touch with the organizing committee by sending an email to rcim@dresd.org


Rationale
It is possible to envision for reconfigurable technologies the possibility to move from the prototyping and very specialized low-volume arenas to the implementation of real-world systems capable of adapting their behaviour and resources thousand times a second, according to the surrounding environment evolution. This capability would widen the horizons of embedded digital systems applications.
At the moment, potential benefits of massively reconfigurable digital systems in real-life applications are still quite far beyond sight, therefore the definition of novel architectures, design flows and last but not least, the creation of a strong community, can be considered as a key point for the future of this research area. To achieve this goal it is necessary to strengthen the Reconfigurable Computing community, trying to promote and support new cooperations between the active actors in this field. It is also important to support the community to encourage new people, institutions and companies to invest and being involved in this area.


Meeting Agenda
The day will be organized according to the following agenda - [Talk]:

09.30 – 9.45 Welcome - D. Sciuto (Politecnico di Milano)

09.45 - 11.30 Session 1: Trends
T1: A. Montanaro (ALTERA) - Altera FPGA strategy for a reconfigurable approach in industry application - [Talk]
T2: F. Campi (STM) - A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing - [Talk]
T3: F. Mantovani (Università di Ferrara) - Janus: FPGA Based System for Scientific Computing - [Talk]
T4: M Corvo (Mindway) - Future Challenge - [Talk]

11.30 – 11.45 Coffee Break

11.45 – 13.15 Session 2: The hArtes European project
T1: R. Nutricato (Atmel Roma) - B2B with minimum TRIMM time. Un obiettivo ambizioso, ma realizzabile - [Talk]
T2: F. Ferrandi (Politecnico di Milano) - PandA: a framework for task partitioning of reconfigurable MPSoCs architectures - [Talk]
T3: G. Marchiori (Università di Ferrara) - The hardware application platform of the hArtes project - [Talk]

13.15 – 14.15 Lunch

14.15 – 15.30 Session 3: Applicative scenarios
T1: F. Cancarè (Politecnico di Milano) - Evolvable Hardware: past, present and future - [Talk]
T2: M. Lanuzza (Università della Calabria) - Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing - [Talk]
T3: A. V. Taddeo (ALaRI) - Coordinated Management of Hardware and Software Self-adaptivity - [Talk]

15.30 – 15.45 Coffee Break

15.45 – 17.30 Session 4: The High Level Reconfiguration project description
T1: F. Redaelli (Politecnico di Milano) - HLR overview - [Talk]
T2: M. Redaelli (Politecnico di Milano) and R. Cordone (Università degli Studi di Milano) - Core Identification for Reconfigurable Systems driven by Specification Self-Similarity - [Talk]
T3: R. Cordone (Università degli Studi di Milano) and F. Redaelli (Politecnico di Milano) - Task Scheduling Techniques on Dynamically Reconfigurable Systems - [Talk]
T4: M. Morandi (Politecnico di Milano) and M. Novati (Politecnico di Milano) - Runtime core relocation management for self dynamically reconfigurable architectures - [Talk]

17.30 - 17.45 Concluding session

With the technical support of the IEEE Italian Section, an the IEEE Computer Society and IEEE Computational Intelligence Society Italian Chapters

Sponsored by: ALTERA, Atmel

Supported by: the Dipartimento di Elettronica ed Informazione (Politecnico di Milano), HiPEAC and the ICT Institute Politecnico di Milano