Information: info@dresd.org

Keywords:

Abstract:

This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Soft Errors in such class of device platforms. We propose an exploration of the design space with respect to several parameters (e.g., area and recovery time) in order to select the most convenient way to apply this technique to the device under consideration. The application to a case study is presented and used to exemplify the proposed approach.

URL:

Keywords:

Abstract:

This paper presents a methodology for designing reliable systems implemented on Field Programmable Gate Arrays (FPGAs), able to cope with the effects of Single Event Upset (SEU) faults, causing bit-flips in SRAM memory. The approach exploits FPGAs’ partial dynamic re-configuration capability to mitigate the effects of SEUs, affecting either the user SRAM memory or the configuration memory itself.
The goal is to detect the occurrence of faults and either to restart computation or to trigger a reconfiguration of part of the device in order to recover from them. The proposal allows the exploration of different solutions, characterized by varying costs and benefits, allowing the designer to select the most convenient trade-off. Results of the application of the methodology to a case study are reported to evaluate the proposed approach.

Keywords:

Abstract:

This paper discusses innovative approaches to design digital systems on SRAM-based FPGAs able to cope with Single Event Upset and Single Event Transient faults by exploiting the opportunities offered by partial dynamic reconfiguration. We present an overview of the strategies we are pursuing in order to use error detection techniques coupled with the reconfiguration to mitigate the effects of such faults by acting only on the portion of the device affected by the fault.