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The context where Polaris finds its rationale, is a self, partial and dynamical reconfiguration scenario, in both its mono-dimensional and bi-dimensional paradigms. In a partially reconfigurable system the functionality of a fraction of the total configurable logic can be changed according to the user's needs, while leaving the rest of the reconfigurable device unchanged. A dynamically reconfigurable system allows this partial change to happen while the rest of the system keeps performing computation. Furthermore, a self reconfigurable system is completely independent from the outside in its management, thus it has to internally host reconfiguration management functionalities, such as task allocation, and to store or be able to autonomously obtain configuration bitstreams when needed.
The 1D reconfiguration paradigm only allows the dynamical reconfiguration of columns spanning the whole device vertically (it can be a 2D placement constraints scenario but without placement overlaps over the x axis), while the 2D paradigm gives the possibility of configuring fractions of the FPGA of arbitrary rectangular shape; the 2D approach is more powerful because of added flexibility but is also more complex to manage. Self partial and dynamical reconfiguration is a powerful approach to reconfiguration, providing flexibility and possibility for high performances, but has the drawback of an increased complexity in reconfigurable system management when compared to simpler approaches; this becomes even more relevant when also exploiting the 2D paradigm.
Goal of Polaris is the creation of a complete workflow to help the designer in the creation and management of self partially and dynamically reconfigurable systems. The provided support is related to the definition of area constraints for tasks, the creation of an efficient runtime task allocation manager and finally the generation of a solution to obtain internal and fast relocation of tasks.
For a general overview of the Polaris project, please download the PPT and/or the PDF Polaris presentation.