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V. Rana, D. A. Atienza, M. D. Santambrogio, D. Sciuto, G. De Micheli,
A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication,
, 16th International Conference on Very Large Scale Integration, IFIP VLSI-SoC 2007, pp. To appear, 10/2008.
Abstract

F. Bruschi, A. Meroni, V. Rana, M. D. Santambrogio,
A Requirements-Driven Simulation Framework For Communication Infrastructures Design,
, In Proceedings of FDL'08 - Forum on specification & Design Languages Stuttgar, pp. To appear, 09/2008.
Abstract

S. Corbetta, V. Rana, M. D. Santambrogio,
A Light-Weight Network-on-Chip Architecture for Dynamically Reconfigurable Systems,
, In Proceedings of IEEE IC-SAMOS'08 - Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos, pp. To Apper, 07/2008.
Abstract

C. A. Curino, M. D. Santambrogio, D. Sciuto,
Research meets Education: DRESD, a virtuous circle,
, 7th European Workshop on Microelectronics Education - EWME 08, pp. To Appear, 05/2008.
Abstract

M. Morandi, M. Novati, M. D. Santambrogio, D. Sciuto,
Core allocation and relocation management for a self dynamically reconfigurable architecture,
, IEEE Computer Society Annual Symposium on VLSI, ISVLSI 07, pp. 286 - 291, 04/2998.
Abstract

M. Paolieri, I. Bonesana, M. D. Santambrogio,
An adaptable FPGA-based System for Regular Expression Matching,
, Design, Automation and Test in Europe, DATE 08, pp. 1262 - 1267, 03/2008.
Abstract

F. Redaelli, M. D. Santambrogio, D. Sciuto,
Task scheduling with configuration prefetching and anti-fragmentation techniques on dynamically reconfigurable systems,
, Design, Automation and Test in Europe, DATE 08, pp. 519 - 522, 03/2008.
Abstract

A. Montone, M. D. Santambrogio, D. Sciuto,
A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems,
, 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 08, pp. 450 - 453, 2008  .

A. Cuoccio, P. R. Grassi, V. Rana, M. D. Santambrogio, D. Sciuto,
A Generation Flow for Self-Reconfiguration Controllers Customization,
, 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 08, pp. 279 - 284, 2008  .
Abstract

A. Meroni, V. Rana, M. D. Santambrogio, D. Sciuto,
A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow,
, 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 08, pp. 405 - 409, 2008  .
Abstract

F. Cancarè, M. D. Santambrogio, D. Sciuto,
A Design Flow Tailored for Self Dynamic Reconfigurable Architecture,
, 22th IEEE International Parallel and Distributed Processing Symposium (IPDPS'08) - Reconfigurable Architecture Workshop - RAW, pp. To appear, 2008  .
Abstract

M. D. Santambrogio, D. Sciuto,
Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign,
, 22th IEEE International Parallel and Distributed Processing Symposium (IPDPS'08) - Reconfigurable Architecture Workshop - RAW, pp. To appear, 2008  .
Abstract

A. Montone, V. Rana, M. D. Santambrogio, D. Sciuto,
HARPE: a Harvard-based ProcessingSantambrogio Tailored for Partial Dynamic Reconfigurable Architectures,
, 22th IEEE International Parallel and Distributed Processing Symposium (IPDPS'08) - Reconfigurable Architecture Workshop - RAW, pp. To appear, 2008  .
Abstract

M. D. Santambrogio, V. Rana, D. Sciuto,
Operating System Support for Online Partial Dynamic Reconfiguration Management,
, 18th International Conference on Field Programmable Logic and Applications, FPL 08, pp. To appear, 2008  .
Abstract

C. A. Curino, L. Fossati, V. Rana, F. Redaelli, M. D. Santambrogio, D. Sciuto,
The Shining embedded system design methodology based on self dynamic reconfigurable architectures,
, 13th ASP-DAC 2008, 13th Asia and South Pacific Design Automation Conference, ASP-DAC 08, pp. 595 - 600, 2008  .
Abstract

C. Bolchini, A. Miele, M. D. Santambrogio,
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs,
, 22nd DFT 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, pp. 87-95, September.
Abstract

V. Rana, C. Sandionigi, M. D. Santambrogio, D. Sciuto,
An adaptive genetic algorithm for dynamically reconfigurable modules allocation,
, 15th IFIP VLSI-SOC 2007, 15th International Conference on Very Large Scale Integration, pp. 128-133, October.
Abstract

M. Paolieri, I. Bonesana, M. D. Santambrogio,
ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching,
, 15th IFIP VLSI-SOC 2007, 15th International Conference on Very Large Scale Integration, pp. 19-24, October.
Abstract

M. D. Santambrogio, V. Rana, S. Ogrenci Memik, D. Sciuto,
A Novel SoC Design Methodology Combining Adaptive Software and Reconfigurable Hardware,
, 25th IEEE/ACM ICCAD 2007, 25th International Conference on Computer-Aided Design, pp. 303 - 308, November.
Abstract

V. Rana, M. D. Santambrogio, D. Sciuto,
Dynamic Reconfigurability in Embedded System Design,
, ISCAS 2007, IEEE International Symposium on Circuits and Systems, pp. 2734-2737, May.
Abstract

V. Rana, C. Sandionigi, M. D. Santambrogio,
A genetic algorithm based solution for dynamically reconfigurable modules allocation,
, 3rd SPL 2007, 3rd Southern Conference on Programmable Logic, pp. 183-186, February.
Abstract

A. Antola, M. D. Santambrogio, M. Fracassi, P. Gotti, C. Sandionigi,
A novel hardware/software codesign methodology based on dynamic reconfiguration with ImpulseC and CoDeveloper,
, 3rd SPL 2007, 3rd Southern Conference on Programmable Logic, pp. 221-224, February.
Abstract

C. Bolchini, C. Brandolese, L. Frigerio, V. Rana, F. Salice, M. D. Santambrogio,
RoadRunner and IPGen: a combined solution to speedup the reconfigurable architectures design,
, 3rd SPL 2007, 3rd Southern Conference on Programmable Logic, pp. 75-78, February.
Abstract

A. Montone, V. Rana, M. D. Santambrogio,
Data memory management in partial dynamically reconfigurable systems,
, 3rd ICIIS 2007, 3rd International Conference on Information System Security, pp. 130, August.
Abstract

A. Antola, M. Castagna, P. Gotti, M. D. Santambrogio,
Evolvable Hardware: a Functional Level Evolution Framework based on Impulse C,
, ERSA 2007, International Conference on Engineering of Reconfigurable Systems & Algorithm, pp. 216-219, 06/2007.
Abstract