<?xml version="1.0" encoding="utf-8"?>
<rss version="2.0" xml:base="http://www.dresd.org" xmlns:dc="http://purl.org/dc/elements/1.1/">
<channel>
 <title>Groups directory</title>
 <link>http://www.dresd.org/og/all</link>
 <description>groups directory</description>
 <language>en</language>
<item>
 <title>Caronte</title>
 <link>http://www.dresd.org/caronte</link>
 <description>&lt;p&gt;&lt;center&gt;&lt;b&gt;&lt;br /&gt;
Please, note that this page is still under construction!&lt;br /&gt;
Stay tuned! It will be available soon!&lt;br /&gt;
&lt;/b&gt;&lt;/center&gt;&lt;/p&gt;


&lt;br class=&quot;clear&quot; /&gt;</description>
 <pubDate>Tue, 22 May 2007 20:07:30 +0200</pubDate>
 <dc:creator>admin</dc:creator>
 <guid isPermaLink="false">158 at http://www.dresd.org</guid>
</item>
<item>
 <title>CITiES</title>
 <link>http://www.dresd.org/cities</link>
 <description>&lt;p&gt;Recent advances in VLSI technology show the limits of the classical computation-centric design paradigm. The ever increasing level of integration and complexity in digital electronic systems requires a communication-centric approach for designing high performance systems, where integrable modules (IP-Cores) require high levels of communication. Classical approaches like bus or point-to-point interconnects are no longer sufficient to ensure and support communication requirements.&lt;/p&gt;


&lt;br class=&quot;clear&quot; /&gt;&lt;p&gt;&lt;a href=&quot;http://www.dresd.org/cities&quot;&gt;read more&lt;/a&gt;&lt;/p&gt;</description>
 <pubDate>Tue, 22 May 2007 22:13:43 +0200</pubDate>
 <dc:creator>admin</dc:creator>
 <guid isPermaLink="false">166 at http://www.dresd.org</guid>
</item>
<item>
 <title>HERA</title>
 <link>http://www.dresd.org/hera</link>
 <description>&lt;p&gt;&lt;center&gt;&lt;b&gt;&lt;br /&gt;
Please, note that this page is still under construction!&lt;br /&gt;
Stay tuned! It will be available soon!&lt;br /&gt;
&lt;/b&gt;&lt;/center&gt;&lt;/p&gt;


&lt;br class=&quot;clear&quot; /&gt;</description>
 <pubDate>Mon, 01 Oct 2007 14:53:44 +0200</pubDate>
 <dc:creator>fabio.cancare</dc:creator>
 <guid isPermaLink="false">468 at http://www.dresd.org</guid>
</item>
<item>
 <title>HLR</title>
 <link>http://www.dresd.org/hlr</link>
 <description>&lt;p&gt;&lt;center&gt;&lt;b&gt;&lt;br /&gt;
Please, note that this page is still under construction!&lt;br /&gt;
Stay tuned! It will be available soon!&lt;br /&gt;
&lt;/b&gt;&lt;/center&gt;&lt;/p&gt;


&lt;br class=&quot;clear&quot; /&gt;</description>
 <pubDate>Sun, 24 Jun 2007 15:26:42 +0200</pubDate>
 <dc:creator>admin</dc:creator>
 <guid isPermaLink="false">308 at http://www.dresd.org</guid>
</item>
<item>
 <title>OSyRiS</title>
 <link>http://www.dresd.org/osyris</link>
 <description>&lt;p&gt;&lt;center&gt;&lt;b&gt;&lt;br /&gt;
Please, note that this page is still under construction!&lt;br /&gt;
Stay tuned! It will be available soon!&lt;br /&gt;
&lt;/b&gt;&lt;/center&gt;&lt;/p&gt;


&lt;br class=&quot;clear&quot; /&gt;</description>
 <pubDate>Fri, 18 May 2007 23:21:30 +0200</pubDate>
 <dc:creator>admin</dc:creator>
 <guid isPermaLink="false">23 at http://www.dresd.org</guid>
</item>
<item>
 <title>Polaris</title>
 <link>http://www.dresd.org/polaris</link>
 <description>&lt;p&gt;The context where &lt;b&gt;Polaris&lt;/b&gt; finds its rationale, is a &lt;b&gt;self, partial and dynamical reconfiguration&lt;/b&gt; scenario, in both its &lt;i&gt;mono-dimensional&lt;/i&gt; and &lt;i&gt;bi-dimensional&lt;/i&gt; paradigms. In a partially reconfigurable system the functionality of a fraction of the total configurable logic can be changed according to the user&#039;s needs, while leaving the rest of the reconfigurable device unchanged. A dynamically reconfigurable system allows this partial change to happen while the rest of the system keeps performing computation.&lt;/p&gt;


&lt;br class=&quot;clear&quot; /&gt;&lt;p&gt;&lt;a href=&quot;http://www.dresd.org/polaris&quot;&gt;read more&lt;/a&gt;&lt;/p&gt;</description>
 <pubDate>Tue, 22 May 2007 22:09:35 +0200</pubDate>
 <dc:creator>admin</dc:creator>
 <guid isPermaLink="false">164 at http://www.dresd.org</guid>
</item>
<item>
 <title>R4R</title>
 <link>http://www.dresd.org/r4r</link>
 <description>&lt;p&gt;
&lt;span class=&quot;inline left&quot;&gt;&lt;img src=&quot;/files/images/r4r.png&quot; alt=&quot;R4R Logo: R4R Logo&quot; title=&quot;R4R Logo: R4R Logo&quot; class=&quot;image thumbnail&quot; /&gt;&lt;/span&gt;&lt;br /&gt;
This project takes its first steps from the opportunity to put together the experience of the past years in the design of digital systems with  dependability properties and the fast evolving research in the field of dynamic reconfiguration of FPGA devices.&lt;/p&gt;


&lt;br class=&quot;clear&quot; /&gt;&lt;p&gt;&lt;a href=&quot;http://www.dresd.org/r4r&quot;&gt;read more&lt;/a&gt;&lt;/p&gt;</description>
 <pubDate>Sun, 20 May 2007 16:58:05 +0200</pubDate>
 <dc:creator>admin</dc:creator>
 <guid isPermaLink="false">88 at http://www.dresd.org</guid>
</item>
<item>
 <title>VALERIE</title>
 <link>http://www.dresd.org/valerie</link>
 <description>&lt;p&gt;&lt;center&gt;&lt;b&gt;&lt;br /&gt;
Please, note that this page is still under construction!&lt;br /&gt;
Stay tuned! It will be available soon!&lt;br /&gt;
&lt;/b&gt;&lt;/center&gt;&lt;/p&gt;


&lt;br class=&quot;clear&quot; /&gt;</description>
 <pubDate>Mon, 01 Oct 2007 17:21:25 +0200</pubDate>
 <dc:creator>admin</dc:creator>
 <guid isPermaLink="false">24 at http://www.dresd.org</guid>
</item>
</channel>
</rss>
