Information: info@dresd.org

.:: Motivation and goals ::.

In this project we are considering multi-FPGAs, reconfiguration and system description portability as the processes of specifying and modeling a complete system before it is partitioned and committed to a style/flow of implementation, attempting to obtain a solution which gives the optimal cost, according to a user defined quality of service value, and performance for the application. In this project, the main emphasis is on correctness and dependability of joining technologies in the hardware and software domains, on the reconfigurable hardware characteristics, on the heterogeneous architectural description, on the satisfaction of quality of service constraints and, in general, on the exploration of the solution space, in order to evaluate the most effective solutions that are compatible.

The main goal of this work is the definition of an environment able to serve several applications sharing the same heterogeneous multi-FPGAs physical architecture. In order to meet this goal several aspects need to be taken under consideration i.e. multi-FPGAs solution Vs reconfigurable one, how to characterized the underlying environment to permit the correct application mapping over it.

.:: Contributions and Results ::.

We can identify several contributions provided by this work:

a) Context definition and characterization:
a.1) Design a set of architectural templates used to define different architectural scenarios i.e. reconfigurable architecture, self reconfigurable architecture, multi-FPGAs architecture, multi-processors architecture etc. etc.. that will be used, according to their characterization to find the best implementation for a specific architecture, required at a specific time.
a.2) Define a way to characterize the incoming application according to their specific needs.
a.3) Model the heterogeneous multi-FPGAs physical architecture in a way that will allow us to have specific characterization of the status of the underlying physical architecture in a fixed runtime time-window.

b) Code portability: in an heterogeneous environment where the quality of service can be measured also in time it is crucial to provide a solution able to speedup the overall implementation phase considering that the same application may need to be completely re-designed and re-implemented if executed using different architectures. In such a context the ability to provide a sort of intermediate portable code able to guarantee the quality of the performances without requiring to re-implement from scratch the entire application, will lead to a significant speedup in the design time and hopefully can bring to a sort of just in time synthesis scenario.

c) Isomorphic sub-graphs identification: the identification of a set of common isomorphic sub-graphs between different applications will provide less reconfigurations to switch from an application to a second one. Therefore, maximizing the isomorphism between applications will lead to a speedup of the swapping time among applications. This technique, combined with the code portability one, will dramatically decrease the synthesis time required to compute the necessary reconfiguration bitstream for an application that has to be executed in a specific configuration of the physical architecture.

Last but not least, due to the analysis done for the heterogeneous multi-FPGAs environment we had been able to identify other applicative scenarios where some of the techniques/methodologies seems to be promising i.e. the code portability in a smart-transportation environment.

.:: Involved Institutes ::.

.:: Northwestern University
.:: Politecnico di Milano



.:: DRESD documentation about this topic ::.

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