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Riconfigurazione dinamica parziale di FPGA per la correzione di guasti SEU: analisi dello spazio delle soluzioni

Source:

DEI, Politecnico di Milano (2007)

Notes:

For the pdf of the thesis, send an email to info@dresd.org


AttachmentSize
IT_BolliBordoni_2007_TesiSlide.pdf2.97 MB
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