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Techniques for Fully Integrated Embedding of Design and Verification Logic for Trusted FPGA Circuits
Fri, 04/03/2009 - 17:18 — admin
Source:
UIC (2008)Notes:
For the pdf of the thesis, send an email to info@dresd.org
| Attachment | Size |
|---|---|
| ENG_MarcoMaggioni_2008_ThesisSlides.ppt | 2.12 MB |
Are you looking for more information? Send an email to: info@dresd.org
This work is licensed under a Creative Commons Attribution-Share Alike 2.5 Italy License
This work is licensed under a Creative Commons Attribution-Share Alike 2.5 Italy License
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