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Core allocation and relocation management for a self dynamically reconfigurable architecture

Mon, 08/11/2008 - 11:17 — admin

Authors:

M. Morandi; M. Novati; M. D. Santambrogio; D. Sciuto

Source:

IEEE Computer Society Annual Symposium on VLSI, ISVLSI 07, p.286 - 291 (2008)

URL:

http://csdl2.computer.org/persagen/DLAbsToc.jsp?resourcePath=/dl/proceedings/&toc=comp/proceedings/isvlsi/2008/3170/00/3170toc.xml&DOI=10.1109/ISVLSI.2008.39

Keywords:

earendil; polaris; tam; birf; 2008

Abstract:

Self, partial and dynamical reconfiguration, in both its mono-dimensional (1D) and bi-dimensional (2D) paradigms, gives the possibility of enhancing the flexibility of a reconfigurable system. It is a powerful approach but, at the same time, causes a significant increase in the complexity of system creation and management. The 1D paradigm allows the dynamical reconfiguration of columns spanning the whole device vertically; the 2D paradigm, on the other hand, allows the reconfiguration area of fractions of arbitrary rectangular shape. The 2D approach is more powerful because of the added flexibility but also require a more complex management. The goal of this paper is to present a complete workflow to support the designer in creating and managing such systems, specifically in the identification of the online cores placement and in the core relocation support. This paper presents a solution able to combine the online cores placement with the runtime bitstreams relocation to implement a complete solution that can be used in conjunction with the runtime self reconfiguration. The validation phase presents the results obtained in placement management and relocation, compared to the results obtained by the state of art solutions to this problem.