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Abstract:

This paper discusses innovative approaches to design digital systems on SRAM-based FPGAs able to cope with Single Event Upset and Single Event Transient faults by exploiting the opportunities offered by partial dynamic reconfiguration. We present an overview of the strategies we are pursuing in order to use error detection techniques coupled with the reconfiguration to mitigate the effects of such faults by acting only on the portion of the device affected by the fault.