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IPGen

IP-Core Generator framework


Please, note that this page is still under construction!
Stay tuned! It will be available soon!



.:: Project Description ::.




.:: Involved Institutes ::.

.:: Politecnico di Milano



.:: DRESD documentation about this project ::.

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2007
C. Bolchini, C. Brandolese, L. Frigerio, V. Rana, F. Salice, M. D. Santambrogio,
RoadRunner and IPGen: a combined solution to speedup the reconfigurable architectures design,
, 3rd SPL 2007, 3rd Southern Conference on Programmable Logic, pp. 75-78, February.
Abstract
2006
M. Murgida, A. Panella, V. Rana, M. D. Santambrogio, D. Sciuto,
Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow,
, 14th IFIP VLSI-SOC 2006, 14th International Conference on Very Large Scale Integration, pp. 74-79, 10/2006.
Abstract
F. Ferrandi, G. Ferrara, R. Palazzo, V. Rana, M. D. Santambrogio,
VHDL to FPGA automatic IPCore generation: A case study on Xilinx design flow,
, 20th IPDPS 2006 Reconfigurable Architecture Workshop (RAW), 20th IEEE International Parallel and Distributed Processing Symposium, pp. 219, 04/2006.
Abstract
Matteo Murgida, Alessandro Panella,
"IPGen: un Framework per la Generazione Automatica di un IP-Core per FPGA",
DEI, Milano, Politecnico di Milano, 2006  .