- No upcoming events available
User login
Syndicate
Events
| Fri | ||
|---|---|---|
Start: 11:00
End: 12:30
Although transistor scaling keeps following Moore`s law, and more area is available for designers, the clock frequency and ILP rate do not grow in the same rate. This way, new architectural alternatives are necessary. | ||
Are you looking for more information? Send an email to: info@dresd.org
This work is licensed under a Creative Commons Attribution-Share Alike 2.5 Italy License
This work is licensed under a Creative Commons Attribution-Share Alike 2.5 Italy License
Search
New Publications
- Studio e realizzazione di controller VGA per sistemi embedded basati su FPGA
- Sistemi embedded sviluppati tramite EDK: implementazione ed analisi delle prestazioni del meccanismo di DMA sul bus OPB
- FLOORPLACEMENT IN DYNAMIC RECONFIGURABLE FPGA-BASED SYSTEMS
- Riconfigurazione dinamica parziale di FPGA per la correzione di guasti SEU: analisi dello spazio delle soluzioni