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The growing needs for computational resources is leading the hardware development community to explore the capabilities of multi-chip systems. Due to the fact that such circuits provide many advantages, they are often preferable to single-chip designs. Low power consumption and parallel computing are only two of the several strengths of multi-chip applications. This trend has shown up also in the field of reprogrammable devices, such that multi-FPGA solutions represent an active and interesting research environment. Multi-chip and multi-core systems are the reaction of the hardware developing community to the growing need of computational power. Nets of general-purpose CPUs are nowadays vastly diffused, while ensembles of ASIC circuits are used in supercomputing applications. The high cost of developing an ad-hoc ASIC circuit make it often unfeasible to create fully-custom multi-chip systems. Therefore reprogrammable logic devices (i.e. FPGAs) represent a suitable technology for implementing such high-performance hardware platforms. The performance and the flexibility of these systems can be slightly improved by adding dynamic reconfigurable capabilities.

In order to exploit extensively the potential of such architectures it is necessary to develop a general high-quality complete workflow for designing multi-FPGA systems. This flow must be capable of producing good designs without the intervention of a human operator during its several phases. Thus the creation of a framework that is able to operate intelligent design choices is needed. This can be considered as the rationale behind DReAMS. The flow is shown in the following Figure.

The framework first parses and partially synthesizes the input VHDL file(s) that describes the application. At this point a partitioning step is required: the application needs to be broken in several chunks, one for each FPGA. The partitioning takes into account the Quality of Service requirements received as input (e.g. throughput, power consumption) and the description of the architecture (e.g. number and dimension of FPGAs, type of communication). The VHDL description of the partitioned application is then generated and validated in order to obtain a feedback for partitioning. This procedure is iterated as long as the QoS requirements are met. After that a co-simulation SystemC/VHDL is carried out. If the feedbacks provided by this simulation are satisfying the bitstreams are generated and the application is downloaded onto FPGAs. The whole workflow must be designed in order to provide a solid basis for supporting dynamic reconfigurability.