Information: info@dresd.org

.:: Project Description ::.

The aim of the project is the definition of an architecture, composed by several IP-Cores and by a communication protocol, that allows data exchanging among FPGAs that represent the nodes of the distributed system. Its development is focused on the flexibility and portability of the architecture, to make it as more independent as possible from the specific kind of board/FPGA on which it will be used. Here a description of each component of a node is given:

.:: Microblaze. This is a soft-processor, beyond running all software tasks needed by the application, it decides when to send a piece of information and how to manage incoming data.

.:: GPIO. This IP-Core represents the interface of the FPGA with the other nodes of the distributed system. It is completely customizable through the proper modification of some parameters called generics in its VHDL description. This component can be adapted to the particular physical link and communication protocol adopted within a specific system providing flexibility to the architecture.

.:: Counter. This component rises an interrupt (called timeout) when it reaches a certain number of clock cycles starting from the last time it has been reset. In this way the communications more robust and deadlock situations are avoided.

.:: Interrupt Controller. This IP-Core has been included in the definition of our architecture with the aim to manage the various interrupts coming from the other cores, including the GPIO and Counter interrupts.

A first prototype of this architecture has been implemented using low cost components as Xilinx Spartan 3 (xc3s200) and Digilent Spartan 3 Starter Board.

We are now working on the definition of a SystemC-VHDL co-simulation framework that will be used to validate the system organization defined using SPartA. This framework will be able to generate the VHDL description that will be used to implement the desired system onto the physical architecture.

.:: Involved Institutes ::.

.:: Politecnico di Milano



.:: DRESD documentation about this project ::.

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