Information: info@dresd.org

.:: Motivation and goals ::.

Reconfigurable hardware is becoming a prominent component in a large variety of SoC designs. Reconfigurability allows for efficient hardware acceleration and virtually unlimited adaptability. On the other hand, overheads associated with reconfiguration and interfaces with the software component need to be evaluated carefully during the exploration phase. The aim of the work done at the Northwestern University was to identify the best trade-off considering application-specific features in software, which can lend itself to software-based acceleration and lead to a revision of the view that certain computationally intensive tasks can only be accelerated through hardware. The proposed methodology addresses the problem of the identification of the software and the hardware components of a complex dynamically reconfigurable SoC, introducing an adaptive computation approach. Adaptivity implies that due to input changes the output of the system is updated only re-evaluating those portions of the program affected by the changes. In order to validate the effectiveness of our proposed techniques, we built an extensive development and experimental setup, bringing together the MLTon-based programming environment and physical mapping of the software and hardware onto a real dynamically reconfigurable SoC system. We present our results and observations on a case study, a frame-based image processing application, that has been implemented by this system.

We proposed a new methodology, based on the Adaptive Programming technique, to evaluate and subsequently perform the hardware and software partitioning for a SoC that employs dynamically reconfigurable hardware and software programmable cores. The main innovation of our technique lies primarily in the way we view and evaluate the software partition. The basic philosophy is the following. If the input to a program is not expected to change significantly over different executions, one can exploit this by introducing the {\it self-adjusting} property into the program such that those computations which do not change across different input sets can be reused instead of being re-executed. This concept has been introduced for exploiting application specific properties in purely software-based systems in order to accelerate execution time by up to three orders of magnitude for various applications. We aim to adapt this paradigm into a mixed hardware and software design flow for reconfigurable SoCs. Our goal is to develop a new performance model and an associated evaluation metric to identify application specific input behavior thereby differentiating between various levels of performance across different portions of software modules. This general performance model is then embedded along with hardware performance models into our proposed environment, which will yield a highly flexible means to evaluate the performance impact of different partitioning and allocation decisions.

.:: Contributions and Results ::.

The specific contributions in this work are as follows. We,

a) developed quantitative evaluation metrics to evaluate the reconfigurable system performance and to represent the performance of software in a SoC from an application-specific, input-oriented point of view,

b) constructed a performance model based on the abovementioned metric,

c) introduced a design environment where the overlapping design space between software and hardware can be explored in greater detail, and

d) presented a case study for a frame-based image processing application on a embedded dynamically reconfigurable SoC architecture

.:: Involved Institutes ::.

.:: Northwestern University
.:: Politecnico di Milano



.::Papers ::.

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